The present invention relates to a packet processing device for performing a predetermined packet process on input packet data in a packet routing device, etc.
Conventionally, communications have been established among terminals interconnected through a network. In view of the growing scale of networks, it has been required to route networks to other networks. For example, a network is set with a LAN (Local Area Network) connected with another LAN, or a LAN connected with a dedicated line. Specifically, a network using an IP (Internet Protocol) has been a leader in this technology. An IP is a connectionless type protocol corresponding to a network layer in an OSI (Open System Interconnection) model of ISO (International Organization for Standardization). In the connectionless type IP communications, unlike the connection type protocol used in reserving in advance a communications path between terminals, a packet routing device for interconnecting LANs realizes the communications among the terminals by performing a routing process on the packets containing communications data. In the routing process in the IP network, it is necessary to perform various packet processes such as a destination table searching process, a header rewriting process, etc.
In the packet process performed in the above mentioned packet routing device, a process of filtering a packet to limit the communications in a network is included in addition to various processes required to route packets such as a process of computing a checksum of a packet header, a process of searching a destination table, a process of rewriting a packet header, etc. These processes are too complicated to be performed using dedicated hardware, and have conventionally been realized in software processes.
FIG. 10 shows the configuration of the conventional packet processing device for performing a packet process using a processor. As shown in FIG. 10, a processor 900 is connected to memory 910 through a bus 920 in the conventional packet processing device. With the configuration, various packet processes are performed in the packet routing device by the processor 900 reading a packet stored in the memory 910.
In the conventional packet processing device using the above mentioned processor 900, packet data has frequently been read and written in the memory 910, it has been difficult to quickly perform the packet process. That is, after the processor 900 stores packet data in the memory 910, the stored packet data is appropriately read, a predetermined process is performed on the read contents, and the process result has to be written to the memory 910. In addition, the processor 900 reads packet data after providing a read address for the memory 910. Similarly, the processor 900 writes packet data after providing a write address for the memory 910. At this time, it takes a longer time to allow data to be read or written after the processor 900 provides an address for the memory 910 than the cycle time of the processor 900.
Furthermore, the consecutive sequence processor 900 can process only one process at a time, and cannot simultaneously perform reading and writing operations. Additionally, it is hard to generate a circuit capable of simultaneously performing reading and writing operations. As a result, the processor 900 cannot simultaneously read and write packet data using the memory 910.
Thus, overhead in reading and writing packet data using the memory 910 is the problem in the process of transferring packet data between the processor 900 and the memory 910, thereby interfering with a high-speed packet process.
In addition, in the conventional packet processing device including the above mentioned processor 900, the processing time allowed for one packet depends on the intervals of consecutively receiving two packets. Therefore, the processing time allowed for the shortest data length of a packet is shortened, thereby causing the problem that the number of steps of executable instruction procedure is smaller. By storing packet data waiting for a process in the memory 910, the processing time can be adjusted when a packet having a short data length is temporarily received, but the memory 910 overflows when a large number of packets having short data lengths are consecutively received, and the number of unprocessed packet data gradually increases. Therefore, a packet processing device is desired which can execute a large number of instruction procedures independently of the type or the data length of a packet if any kind of packet is transferred or received.